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Revision Date Username Comment
4502 Apr 2014 - 16:08BodhisatwaSadhu 
4430 Mar 2014 - 16:31BodhisatwaSadhu 
4322 Jun 2013 - 14:15BodhisatwaSadhu(minor)  
4221 Jun 2013 - 17:19BodhisatwaSadhu(minor)  
4116 Apr 2013 - 17:35BodhisatwaSadhu 
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You are here: UMWiki>Main Web>WikiUsers>BodhisatwaSadhu (02 Apr 2014, BodhisatwaSadhu)
Bodhisatwa Sadhu

Bodhisatwa Sadhu

Research Staff Member at IBM T.J. Watson Research Center

Email: sadhu@us.ibm.com

I am currently a Post-doctoral researcher at IBM T. J. Watson Research Center working in the Communication Circuits and Systems department. I am interested in analog, mixed-signal and RF integrated circuits, specializing in Cognitive Radios and phased array systems.

Education

PhD Electrical Engineering University of Minnesota, Twin Cities 2007 - 2012 GPA: 4.0
BE Electrical and Electronics Engineering Birla Institute of Technology and Science, Pilani 2003 - 2007 GPA: 3.97

Teaching

EE 8337: Analog Circuits for Wired/Wireless Communications, Spring 2012 EE 3115: Analog & Digital Electronics, Spring 2011
  • Course website
    Differential & multi-stage amplifiers, amplifier stability, filters, logic circuits, CMOS digital circuits

Projects

  • A 60GHz phased array front-end for communications
  • Low phase noise PLLs for 60GHz and 94GHz phased arrays
  • Spectrum sensing for Cognitive Radios using passive switched capacitors
  • Cognitive radio frequency synthesis using wide tuning range (150% tuning range) single inductor LC VCOs

Publications

Peer reviewed conference publications

  • Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion
    Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Larry Pileggi, Arun Natarajan, Mark Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin Parker, Alberto Valdes-Garcia, Mihai Sanduleanu, Jose Tierno, Daniel Friedman, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2013
  • A 73.9-83.5GHz Synthesizer with -111dBc/Hz Phase Noise at 10MHz Offset in 130nm SiGe BiCMOS
    Jean-Olivier Plouchart, Mark Ferriss, Bodhisatwa Sadhu, Mihai Sanduleanu, Benjamin Parker, Scott Reynolds, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013
  • A Fully-Integrated Dual-Polarization 16-Element W-band Phased-Array Transceiver in SiGe BiCMOS
    Alberto Valdes-Garcia, Arun Natarajan, Duixian Liu, Mihai Sanduleanu, Xiaoxiong Gu, Mark Ferriss, Benjamin Parker, MD R Islam, Christian Baks, Jean-Olivier Plouchart, Herschel Ainspan, Bodhisatwa Sadhu, Scott Reynolds, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013
  • Enhanced Multilayer Organic Packages with Embedded Phased-Array Antennas for 60-GHz Wireless Communications
    Xiaoxiong Gu, Dong Gun Kam, Duixian Liu, Maxim Piz, Alberto Valdes-Garcia, Arun Natarajan, Christian Baks, Bodhisatwa Sadhu and Scott Reynolds, IEEE Electronic Components and Technology Conference (ECTC), May 2013
  • An 8GHz Multi-Beam Spatio-Spectral Beamforming Receiver Using an All-Passive Discrete Time Analog Baseband in 65nm CMOS (paper)
    Satwik Patnaik, Sachin Kalia, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry and Ramesh Harjani, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2012
  • A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS (paper)
    Jean-Olivier Plouchart, Mark Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin Parker, Michael Beakes, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Scott Reynolds, Jose A. Tierno and Daniel Friedman, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2012
  • A 5GS/s 12.2pJ/conv. Analog Charge-Domain FFT for a Software Defined Radio Receiver Front-End in 65nm CMOS (paper)
    Bodhisatwa Sadhu, Martin Sturm, Brian Sadler and Ramesh Harjani, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2012
  • A 21.8−27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve −130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier _(nominated for Best Paper Award)_ (paper)
    Bodhisatwa Sadhu, Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Alberto Valdes-Garcia, Benjamin Parker, Scott Reynolds, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Jose Tierno and Daniel Friedman, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2012
  • Dual Channel Injection-Locked Quadrature LO Generation for a 4GHz Instantaneous Bandwidth Receiver 21GHz Center Frequency (nominated for Best Paper Award) (paper)
    Mohammad Elbadry, Bodhisatwa Sadhu, Joe Qiu and Ramesh Harjani, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2012
  • An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS (paper)
    Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jose Tierno and Daniel Friedman, IEEE Symposia on VLSI Technology and Circuits (VLSI), June 2012
  • A Simple, Unified Phase Noise Model for Injection-Locked Oscillators (paper)
    Sachin Kalia, Mohammad Elbadry, Bodhisatwa Sadhu, Satwik Patnaik, Joe Qiu and Ramesh Harjani, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2011
  • Capacitor Bank Design for Wide Tuning Range LC VCO: 850MHz - 7.1GHz (157%) (among all time top 100 papers on VCO design in IEEE) (paper)
    Bodhisatwa Sadhu and Ramesh Harjani, IEEE International Symposium for Circuits and Systems (ISCAS), May 2010
  • A 3.3 to 8.5 GHz Wideband, Low Phase Noise LC VCO (paper)
    Bodhisatwa Sadhu, Jaehyup Kim and Ramesh Harjani, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2009
  • Modeling and Synthesis of Wide-Band Switched-Resonators for VCOs (paper)
    Bodhisatwa Sadhu, Umaikhe Omole and Ramesh Harjani, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008

Peer reviewed journal publications

  • Dual Channel Injection-Locked Quadrature LO Generation for a 4-GHz Instantaneous Bandwidth Receiver at 21GHz Center Frequency (invited) (paper)
    Mohammad Elbadry, Bodhisatwa Sadhu, Joe Qiu and Ramesh Harjani, IEEE Transactions on Microwave Theory and Techniques, March 2013
  • An Integral Path Self-Calibration Scheme for a Dual-Loop PLL (invited) (paper)
    Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin Parker, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu and Daniel Friedman, IEEE Journal of Solid State Circuits (JSSC), April 2013
  • Analysis and Design of a 5GS/s Analog Charge-Domain FFT for an SDR Front-End in 65nm CMOS (invited) (paper)
    Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler and Ramesh Harjani, IEEE Journal of Solid State Circuits (JSSC), May 2013
  • A Linearized, Low Phase Noise VCO Based 25GHz PLL with Autonomic Biasing (invited, most downloaded paper for JSSC May 2013 publication) (paper)
    Bodhisatwa Sadhu, Mark Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander Rylyakov, Alberto Valdes-Garcia, Benjamin Parker, Aydin Babakhani, Scott Reynolds, Xin Li, Larry Pileggi, Ramesh Harjani, Jose Tierno and Daniel Friedman, IEEE Journal of Solid State Circuits (JSSC), May 2013
  • An 8GHz Multi-Beam Spatio-Spectral Beamforming Receiver Using an All-Passive Discrete Time Analog Baseband in 65nm CMOS (invited) (paper)
    Sachin Kalia, Satwik Patnaik, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry and Ramesh Harjani, IEEE Transactions on Circuits and Systems – I (TCAS-I)
  • A 23.5GHz PLL with an Adaptively Biased VCO in 32nm SOI-CMOS (invited) (paper)
    Jean-Olivier Plouchart, Mark Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin Parker, Michael Beakes, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Scott Reynolds, Jose Tierno and Daniel Friedman, IEEE Transactions on Circuits and Systems – I (TCAS-I)

Patents

  • Fully Decoupled LC Oscillators for Low Phase Noise & High Oscillation Amplitude Applications (patent)
    Bodhisatwa Sadhu, Jean-Olivier Plouchart, Scott Reynolds, Alexander Rylyakov and Jose Tierno, U.S. Patent
  • Switched Capacitor FFT based RF Front-Ends for Low Power, Wideband Applications (filed)
    Ramesh Harjani, Bodhisatwa Sadhu and Martin Sturm, U.S. Patent
  • Current Re-use VCO, Harmonic Generator and Regulator Circuit (disclosure)
    Bodhisatwa Sadhu, Mihai Sanduleanu, Scott K. Reynolds and Alberto Valdes-Garcia, U.S. Patent

Books

  • Cognitive Radio Receiver Front-Ends - RF/Analog Circuit Techniques
    Bodhisatwa Sadhu and Ramesh Harjani, Springer Science and Business Media, Analog Circuits and Signal Processing series, 2013

Invited Talks

  • Transconductance linearization and autonomic biasing for low phase noise VCOs
    Bodhisatwa Sadhu, Columbia University, New York (http://www.cisl.columbia.edu/seminars.html), 2013
  • Circuits for Cognitive Radios: From Concept to Implementation
    Bodhisatwa Sadhu, Cosmic Circuits, Bangalore, 2011
  • An RF FFT Based Architecture for Spectrum Sensing in SDRs
    Bodhisatwa Sadhu, Center for Circuit & System Solutions (C2S2), e-seminar, 2012

Awards & Honors

  • Paper in "Top 100 papers on LC VCOs" in IEEE RFIC journal, 2012
  • UMN Doctoral Dissertation Fellowship, 2011-2012
  • 4-year 3M Fellowship, 2009-2012
  • Graduate School Fellowship, University of Minnesota, 2007-2008
  • University Silver Medal for 2nd position in the class of 2007 (1000 students), BITS Pilani
  • BITS Merit Scholarship (100% tuition waiver), 2003-2007
  • First prize winner at Analog Design Contest, APOGEE National Technical Fest, 2006
  • First prize winner at Conquest (all-India competition on entrepreneurial leadership), 2004
  • 2nd rank in India (among 45000 students) in ISC (National High School Final) Examination, 2003

Professional Experience

Jul, 2012 - present Post-doctoral Researcher, IBM T.J. Watson Research Center,Yorktown Heights, USA
Oct, 2011 - Nov, 2011 Research Intern, IBM T.J. Watson Research Center,Yorktown Heights, USA
May, 2011 - Jul, 2011 Research Intern, IBM T.J. Watson Research Center,Yorktown Heights, USA
Aug, 2010 - Dec, 2010 Research Intern, IBM T.J. Watson Research Center,Yorktown Heights, USA
Jan, 2007 - Jul, 2007 Design Engineering Intern, Broadcom Corporation, Bangalore, India
May, 2005 - Jul, 2005 Electronic Engineering Intern, Bhabha Atomic Research Center, Mumbai, India

Graduate Courses

  • EE5333 Analog IC Design (Fall 2007)
  • EE8337 Circuits for Wired and Wireless Communications (Spring 2008)
  • EE5601 Introduction to RF/Microwave Engineering (Spring 2008)
  • EE5501 Digital Communcations (Fall 2007)
  • EE5323 VLSI Design I (Fall 2008)
  • EE5324 VLSI Design II (Spring 2009)
  • EE5327 VLSI Design Laboratory (Spring 2009)
  • EE4541 Digital Signal Processing (Fall 2008)
  • EE5164 Semiconductor Properties and Devices (Spring 2008)
  • EE8283 Problems in CAD (Fall 2009)
  • EE8950 Teaching experience in EE (Spring 2010)
  • MATH4567 Fourier Analysis (Fall 2009)
  • MATH4242 Applied Linear Algebra (Spring 2010)

Hobbies

  • Photography
  • Poetry
  • Sketching
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Topic revision: r45 - 02 Apr 2014 - 16:08:30 - BodhisatwaSadhu
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