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Revision Date Username Comment
5628 Apr 2015 - 11:10BodhisatwaSadhu 
5517 Apr 2015 - 10:17BodhisatwaSadhu 
5402 Apr 2015 - 08:14BodhisatwaSadhu 
5301 Apr 2015 - 21:45BodhisatwaSadhu 
5201 Apr 2015 - 14:18BodhisatwaSadhu(minor)  
5131 Mar 2015 - 15:57BodhisatwaSadhu 
5030 Mar 2015 - 17:14BodhisatwaSadhu 
4916 Feb 2015 - 15:13BodhisatwaSadhu(minor)  
4811 Feb 2015 - 16:29BodhisatwaSadhu 
4723 Oct 2014 - 22:11BodhisatwaSadhu(minor)  
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You are here: UMWiki>Main Web>WikiUsers>BodhisatwaSadhu (28 Apr 2015, BodhisatwaSadhu)
Bodhisatwa Sadhu

Bodhisatwa Sadhu

Research Staff Member at IBM T.J. Watson Research Center

Email: sadhu@us.ibm.com

I am currently a Research Staff member at IBM T.J. Watson Research Center, NY. I received my Ph.D. degree in Electrical Engineering from University of Minnesota, Minneapolis, in 2012 and my B.E. degree in Electrical and Electronics Engineering from BITS, Pilani, India in 2007. For my Ph.D., I worked on wideband circuits and architectures for software defined radio applications. In 2007, I was with Broadcom Corporation, Bangalore, where I worked on system integration and verification of ethernet switch SoCs?. In Fall-2010 and Summer-2011, I was with the Mixed Signal Communications IC Design Group, IBM T.J. Watson Research Center where I worked on the analysis and design of low phase noise frequency synthesizers for 60GHz and 94GHz applications. Since 2012, I have been working on mm-wave transceivers in the RF/mm-wave Communications Circuits group at IBM Research.

Current Projects

Prior Work

  • Scalable 94GHz 64 element phased array for imaging/communications (DARPA SBPAT program)
  • Charge based FFT for spectrum sensing in Cognitive Radios (DARPA CLASIC program)
  • Wide-tuning, low phase noise switched inductor LC VCOs for reconfigurable radios

Peer Reviewed Publications

2015

  • C21 - A Capacitance Boosted Full-Octave LC VCO Based 0.7 to 24GHz Fractional-N Synthesizer (selected for industry showcase) (paper)
    Bodhisatwa Sadhu, Mark Ferriss, Daniel Friedman, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), May 2015
  • C20 - A 3-Band Switched-Inductor LC VCO and Differential Current Re-Use Doubler Achieving 0.7-to-11.6GHz Tuning Range (paper)
    Bodhisatwa Sadhu, Sachin Kalia, Ramesh Harjani, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), May 2015
  • C19 - A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS Technology with Autonomic NF Calibration (paper)
    Jean-Olivier Plouchart, Fa Wang, Andreea Balteanu, Ben Parker, Mihai Sanduleanu, Mark Yeck, Vanessa Chen, Wayne Woods, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Xin Li, Daniel Friedman
  • J12 - A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique that Preserves VCO Performance (invited) (paper)
    Bodhisatwa Sadhu, Mark Ferriss, Alberto Valdes-Garcia, IEEE Journal of Solid State Circuits (JSSC), May 2015
  • J11 - W-band Scalable Phased Arrays for Imaging and Communications (invited) (paper)
    Xiaoxiong Gu, Alberto Valdes-Garcia, Arun Natarajan, Bodhisatwa Sadhu, Duixian Liu, and Scott K. Reynolds, IEEE Communications Magazine, April 2015
  • C18 - A 13GHz to 28GHz Fractional-N PLL in 32nm SOI CMOS with a DS Noise Cancellation Scheme (paper)
    Mark Ferriss, Bodhisatwa Sadhu, Alexander Rylakov, Herschel Ainspan, Daniel Friedman, IEEE International Solid State Circuits Conference (ISSCC), February 2015

2014

  • J10 - Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits (invited) (paper)
    Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin Parker, Mihai Sanduleanu, Andreea Balteanu, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Danier Friedman, IEEE Design & Test, December 2014
  • C17 - Device and Circuit Performance of SiGe HBTs in 130nm BiCMOS process with fT/fMAX of 250/330GHz (paper)
    V. Jain, T. Kessler. B. J. Gross, J. J. Pekarik, P. Candra, P. B. Gray, B. Sadhu, A. Valdes-Garcia, P. Cheng, R. A. Camillo-Castillo, K. Newton, A. Natarajan, S. K. Reynolds, D. L. Harame, IEEE Bipolar/!BiCMOS Circuites and Technology Meeting (BCTM), September 2014
  • C16 - A 90nm SiGe BiCMOS Technology for mm-Wave and High-Performance Analog Applications (paper)
    J. J. Pekarik, J. Adkisson, P. Gray, Q. Liu, R. Camillo-Castillo, M. Khater, V. Jain, B. Zetterlund, A. DiVergilio?, X. Tian, A Vallett, J. Ellis-Monaghan, B. J. Gross, P. Cheng, V. Kaushal, Z. He, J. Lukaitis, K. Newton, M. Kerbaugh, N. Cahoon, L. Vera, Y. Zhao, J. R. Long, A. Valdes-Garcia, S. Reynolds, W. Lee, B. Sadhu, D. L. Harame, IEEE Bipolar/!BiCMOS Circuites and Technology Meeting (BCTM), September 2014
  • J9 - Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits (invited) (paper)
    Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Larry Pileggi, Arun Natarajan, Mark Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin Parker, Alberto Valdes-Garcia, Mihai Sanduleanu, Jose Tierno, Daniel Friedman, IEEE Transactions on Circuits and Systems - I (TCAS-I), August 2014
  • C15 - A 46.4–58.1 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique that Preserves VCO Performance (selected for industry showcase)(paper)
    Bodhisatwa Sadhu, Mark Ferriss, Alberto Valdes-Garcia, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2014
  • J8 - Building an On-chip Spectrum Sensor for Cognitive Radios (invited)(paper)
    Bodhisatwa Sadhu, Martin Sturm, Brian Sadler and Ramesh Harjani, IEEE Communications Magazine, April 2014
  • J7 - Passive Switched Capacitor RF Front-ends for Spectrum Sensing in Cognitive Radio (paper)
    Bodhisatwa Sadhu, Martin Sturm, Brian Sadler and Ramesh Harjani, Hindawi International Journal of Antenna and Propagation (IJAP), 2014

2013

  • C14 - Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion (paper)
    Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Larry Pileggi, Arun Natarajan, Mark Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin Parker, Alberto Valdes-Garcia, Mihai Sanduleanu, Jose Tierno, Daniel Friedman, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2013
  • J6 - Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays (invited) (paper)
    Sachin Kalia, Satwik Patnaik, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry and Ramesh Harjani, IEEE Transactions on Circuits and Systems – I (TCAS-I), August 2013
  • J5 - A 23.5GHz PLL with an Adaptively Biased VCO in 32nm SOI-CMOS (invited) paper
    Jean-Olivier Plouchart, Mark Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin Parker, Michael Beakes, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Scott Reynolds, Jose Tierno and Daniel Friedman, IEEE Transactions on Circuits and Systems – I (TCAS-I), August 2013
  • C13 - A 73.9-83.5GHz Synthesizer with -111dBc/Hz Phase Noise at 10MHz Offset in 130nm SiGe BiCMOS (paper)
    Jean-Olivier Plouchart, Mark Ferriss, Bodhisatwa Sadhu, Mihai Sanduleanu, Benjamin Parker, Scott Reynolds, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013
  • C12 - A Fully-Integrated Dual-Polarization 16-Element W-band Phased-Array Transceiver in SiGe BiCMOS (paper)
    Alberto Valdes-Garcia, Arun Natarajan, Duixian Liu, Mihai Sanduleanu, Xiaoxiong Gu, Mark Ferriss, Benjamin Parker, MD R Islam, Christian Baks, Jean-Olivier Plouchart, Herschel Ainspan, Bodhisatwa Sadhu, Scott Reynolds, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013
  • C11 - Enhanced Multilayer Organic Packages with Embedded Phased-Array Antennas for 60-GHz Wireless Communications (paper)
    Xiaoxiong Gu, Dong Gun Kam, Duixian Liu, Maxim Piz, Alberto Valdes-Garcia, Arun Natarajan, Christian Baks, Bodhisatwa Sadhu and Scott Reynolds, IEEE Electronic Components and Technology Conference (ECTC), May 2013
  • J4 - A Linearized, Low Phase Noise VCO Based 25GHz PLL with Autonomic Biasing (invited, most downloaded IEEE JSSC paper in 2013) (paper)
    Bodhisatwa Sadhu, Mark Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander Rylyakov, Alberto Valdes-Garcia, Benjamin Parker, Aydin Babakhani, Scott Reynolds, Xin Li, Larry Pileggi, Ramesh Harjani, Jose Tierno and Daniel Friedman, IEEE Journal of Solid State Circuits (JSSC), May 2013
  • J3 - Analysis and Design of a 5GS/s Analog Charge-Domain FFT for an SDR Front-End in 65nm CMOS (invited) (paper)
    Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler and Ramesh Harjani, IEEE Journal of Solid State Circuits (JSSC), May 2013
  • J2 - An Integral Path Self-Calibration Scheme for a Dual-Loop PLL (invited) (paper)
    Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin Parker, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu and Daniel Friedman, IEEE Journal of Solid State Circuits (JSSC), April 2013
  • J1 - Dual Channel Injection-Locked Quadrature LO Generation for a 4-GHz Instantaneous Bandwidth Receiver at 21GHz Center Frequency (invited) (paper)
    Mohammad Elbadry, Bodhisatwa Sadhu, Joe Qiu and Ramesh Harjani, IEEE Transactions on Microwave Theory and Techniques, March 2013

2012

  • C10 - An 8GHz Multi-Beam Spatio-Spectral Beamforming Receiver Using an All-Passive Discrete Time Analog Baseband in 65nm CMOS (paper)
    Satwik Patnaik, Sachin Kalia, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry and Ramesh Harjani, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2012
  • C9 - A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS (paper)
    Jean-Olivier Plouchart, Mark Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin Parker, Michael Beakes, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Scott Reynolds, Jose A. Tierno and Daniel Friedman, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2012
  • C8 - A 5GS/s 12.2pJ/conv. Analog Charge-Domain FFT for a Software Defined Radio Receiver Front-End in 65nm CMOS (paper)
    Bodhisatwa Sadhu, Martin Sturm, Brian Sadler and Ramesh Harjani, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2012
  • C7 - A 21.8−27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve −130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier (nominated for Best Paper Award) (paper)
    Bodhisatwa Sadhu, Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Alberto Valdes-Garcia, Benjamin Parker, Scott Reynolds, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Jose Tierno and Daniel Friedman, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2012
  • C6 - Dual Channel Injection-Locked Quadrature LO Generation for a 4GHz Instantaneous Bandwidth Receiver 21GHz Center Frequency (nominated for Best Paper Award) (paper)
    Mohammad Elbadry, Bodhisatwa Sadhu, Joe Qiu and Ramesh Harjani, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2012
  • C5 - An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS (paper)
    Mark Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jose Tierno and Daniel Friedman, IEEE Symposia on VLSI Technology and Circuits (VLSI), June 2012

2011

  • C4 - A Simple, Unified Phase Noise Model for Injection-Locked Oscillators (paper)
    Sachin Kalia, Mohammad Elbadry, Bodhisatwa Sadhu, Satwik Patnaik, Joe Qiu and Ramesh Harjani, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2011

2010

  • C3 - Capacitor Bank Design for Wide Tuning Range LC VCO: 850MHz - 7.1GHz (157%) (among all time top 100 papers on VCO design in IEEE) (paper)
    Bodhisatwa Sadhu and Ramesh Harjani, IEEE International Symposium for Circuits and Systems (ISCAS), May 2010

2009

  • C2 - A 3.3 to 8.5 GHz Wideband, Low Phase Noise LC VCO (paper)
    Bodhisatwa Sadhu, Jaehyup Kim and Ramesh Harjani, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2009

2008

  • C1 - Modeling and Synthesis of Wide-Band Switched-Resonators for VCOs (paper)
    Bodhisatwa Sadhu, Umaikhe Omole and Ramesh Harjani, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2008

Patents

  • P2 - Fully Decoupled LC Oscillators for Low Phase Noise & High Oscillation Amplitude Applications (patent)
    Bodhisatwa Sadhu, Jean-Olivier Plouchart, Scott Reynolds, Alexander Rylyakov and Jose Tierno, US, UK, Germany, China Patent
  • P1 - Multi-stage Charge Re-use Analog Circuits (patent)
    Ramesh Harjani, Bodhisatwa Sadhu, Martin Sturm, Sachin Kalia and Satwik Patnaik, US Patent

Books & Book Chapters

  • Cognitive Radio Receiver Front-Ends - RF/Analog Circuit Techniques (Springer, Amazon)
    Bodhisatwa Sadhu and Ramesh Harjani, Springer Science and Business Media, Analog Circuits and Signal Processing series, 2013
  • Analog Signal Processing for Reconfigurable Receiver Front-Ends (CRC Press, Amazon)
    Bodhisatwa Sadhu and Ramesh Harjani, in Wireless Transceiver Circuits, editor: Woogeun Rhee, CRC Press, 2014

Invited Talks

  • Low-noise mm-Wave Frequency Synthesis Techniques in Silicon
    Bodhisatwa Sadhu, IEEE RFIC Workshop on Frequency Synthesis for 60GHz and Beyond: Architecture and Building Blocks, Tampa, FL, June 2014
  • Transconductance linearization and autonomic biasing for low phase noise VCOs
    Bodhisatwa Sadhu, Columbia University, New York (http://www.cisl.columbia.edu/seminars.html), 2013
  • An RF FFT Based Architecture for Spectrum Sensing in SDRs
    Bodhisatwa Sadhu, Center for Circuit & System Solutions (C2S2), e-seminar, 2012
  • Circuits for Cognitive Radios: From Concept to Implementation
    Bodhisatwa Sadhu, Cosmic Circuits, Bangalore, 2011

Teaching

UMN EE 8337: Circuits for Wired/Wireless Communications, Spring 2012 UMN EE 3115: Analog & Digital Electronics, Spring 2011
  • Course website
    Differential & multi-stage amplifiers, amplifier stability, filters, logic circuits, CMOS digital circuits

Education

PhD Electrical Engineering University of Minnesota, Twin Cities 2007 - 2012 GPA: 4.0
BE Electrical and Electronics Engineering Birla Institute of Technology and Science, Pilani 2003 - 2007 GPA: 3.97

Professional Experience

Mar, 2014 - present Research Staff Member, IBM T.J. Watson Research Center,Yorktown Heights, USA
Jul, 2012 - Feb, 2014 Post-doctoral Researcher, IBM T.J. Watson Research Center,Yorktown Heights, USA
Oct, 2011 - Nov, 2011 Research Intern, IBM T.J. Watson Research Center,Yorktown Heights, USA
May, 2011 - Jul, 2011 Research Intern, IBM T.J. Watson Research Center,Yorktown Heights, USA
Aug, 2010 - Dec, 2010 Research Intern, IBM T.J. Watson Research Center,Yorktown Heights, USA
Jan, 2007 - Jul, 2007 Design Engineering Intern, Broadcom Corporation, Bangalore, India
May, 2005 - Jul, 2005 Electronic Engineering Intern, Bhabha Atomic Research Center, Mumbai, India

Awards & Honors

  • IBM Second Plateau Invention Achievement Award, 2015
  • IBM First Plateau Invention Achievement Award, 2014
  • IBM First Patent Application Award, 2013
  • LiTVCO paper most downloaded IEEE JSSC paper, 2013
  • VCO Paper in "Top 100 papers on LC VCOs" in IEEE RFIC journal, 2012
  • UMN Doctoral Dissertation Fellowship, 2011-2012
  • 4-year 3M Science and Technology Fellowship, 2009-2012
  • Graduate School Fellowship, University of Minnesota, 2007-2008
  • University Silver Medal for 2nd position in the class of 2007 (1000 students), BITS Pilani
  • BITS Pilani Merit Scholarship (100% tuition waiver), 2003-2007
  • First prize winner at Analog Design Contest, APOGEE National Technical Fest, 2006
  • First prize winner at Conquest (all-India competition on entrepreneurial leadership), 2004
  • 2nd rank in India (among 45000 students) in ISC (National High School Final) Examination, 2003

Hobbies

  • Photography
  • Poetry
  • Sketching
  • Cricket

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Topic revision: r56 - 28 Apr 2015 - 11:10:31 - BodhisatwaSadhu
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