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Revision Date Username Comment
1214 Nov 2011 - 10:15SudhirKudvaAttached file Sudhir.jpg 
1101 Oct 2011 - 13:50SudhirKudva 
1030 Apr 2011 - 11:48SudhirKudva 
921 Feb 2011 - 17:32SudhirKudva 
826 Jan 2011 - 10:25SudhirKudva 
718 Jan 2011 - 13:54SudhirKudva 
617 Jan 2011 - 12:01SudhirKudva 
512 Jan 2011 - 16:58SudhirKudva 
410 Jan 2011 - 16:58SudhirKudva 
306 Jan 2011 - 16:57SudhirKudva(minor)

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Sudhir S. Kudva

Department of Electrical and Computer Engineering
University of Minnesota, Twin Cities
4-156
200 Union Street SE
Minneapolis
MN 55455
Email : kudva003 [at] umn [dot] edu

Education

PhD Electrical Engineering University of Minnesota, Twin Cities 2008 - 2013 (Expected)
M.S Microelectronics Indian Institute of Science, Bangalore, India 2004 - 2006
B.E. Electronics and Communications Engineering National Institute of Technology Karnataka, Suratkal, India 2000 - 2004

Work Experience

Aug, 2006 - July, 2008 Design Engineer II, AMD, India
May, 2011 - Aug, 2011 Graduate Technical Intern, Intel Labs, Oregon, US

Projects

  • High Efficiency on-chip DC-DC converter design – Designed a DC-DC Experience converter to supply power from 0.6mW to 266mW at high efficiency in 130nm IBM CMOS process.
  • Design of LNA and Mixer - Design of very low power LNA and Mixer compliant with Zigbee standard in UMC 130nm process

Publications

  • "A Zero-Area, Zero-Power Supply Resonance Reduction Technique", Sudhir S. Kudva, Ramesh Harjani, Techcon, September 2011.
  • "Fully Integrated On-Chip DC-DC Converter with a 450x Output Range", Sudhir S. Kudva, Ramesh Harjani, (invited) in IEEE Journal of Solid-State Circuits, for the CICC August special issue 2011
  • “Fully Integrated On-Chip DC-DC Converter with a 450x Output Range”, Sudhir S. Kudva, Ramesh Harjani, IEEE Custom Integrated Circuits Conference (CICC), September 2010.
  • “Inductors Above Digital Circuits: Towards Compact On-Chip Switching Regulators”, Sudhir S. Kudva, Ramesh Harjani, Techcon, September 2010.
  • “A Low-Power Frequency Multiplication Technique for ZigBee? Transciever”, Jagdish Narayan Pandey, Sudhir S. Kudva and Bharadwaj Amrutur, IEEE VLSI Design Conference, December 2007.
  • “A Low-Power, Low-Noise amplifying Mixer for ZigBee? Reciever”, Sudhir S. Kudva, Jagdish Narayan Pandey and Bharadwaj Amrutur, was ranked in top 10 in Cadence Design Contest , October 2006.
  • “Quality and Complexity Comparison of H.264 Intramode with JPEG2000 and JPEG”, Aravind AL., Bindu P. Rao, Sudhir S. Kudva, Sreenu Babu, Sumam David, Ajit V. Rao, International Conference in Image Processing(ICIP), October 2004.

Patent

  • "Data Processing Device and Methods Thereof", Srinivasan Srinath, Sudhir Kudva, Joel T. Irby, Patent No # 7,724,015 B2

Course Work

  • EE5323 VLSI Design I (Fall 2008)
    • Project: Design of a 16-bit Brent Kung Adder
  • EE5333 Analog IC Design (Fall 2008)
    • Project: Implementation of a Part of the Automatic Gain Control Loop
  • EE5163 Semiconductor Properties and Devices I (Fall 2008)
    • Term Paper: Strain Engineering for Mobility Enhancement in Si based MOSFETs
  • EE5601 Introduction to RF/Microwave Engineering (Spring 2009)
    • Project: Design of Preselect filter (Zigbee standard)
  • CS8283 Research Problems in Computer-Aided Design for Electronic Design (Fall 2009)
    • Term Paper: Phase change memory
  • EE8337 Analog Circuits for wireless communications (Spring 2010)
    • Project: Design of differential LNA and Mixer

Hobbies

  • Badminton
  • Politics
  • Movies

Resume

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Topic revision: r12 - 14 Nov 2011 - 10:15:49 - SudhirKudva
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